1. Field of the Invention
The present invention relates generally to a semiconductor memory device and a method of manufacturing the same, and more particularly to a trench DRAM with a double-gated transistor and a method of manufacturing the same.
2. Description of the Related Art
In these years, with a trend of accelerated increase in integration density of DRAMs, the cell size has decreased more and more and also the gate length of the cell transistor has decreased more and more. In a DRAM (Dynamic Random Access Memory) cell, in order to maintain retention characteristics of charge accumulated in the capacitor, it is necessary to control a sub-threshold current, a junction leakage current and a GIDL (Gate Induced Drain Leakage) current of the cell transistor. In particular, in order to suppress the sub-threshold current, it is necessary to set the threshold voltage of the cell transistor at a high level.
On the other hand, a decrease in threshold voltage caused by a short-channel effect due to reduction in gate length needs to be corrected by an increase in channel dosage. This results in an increase in junction leakage current and a degradation in electron channel mobility. The former deteriorates the retention characteristics of the DRAM, and the latter prevents improvement in drive-current of the cell transistor in fabricating a high-speed DRAM. In particular, with reduction in cell size, the channel width W, which is an important parameter for determining the drive-current of the cell transistor, decreases and the drive-current further decreases.
As an effective methods for solving the above problems, a double-gated transistor has been proposed (e.g. Jpn. Pat. Appln. KOKAI Publication No. 2002-118255). In addition, double-dated transistors have recently been published by academic societies, etc. (e.g. Dai Hisamoto, et al., IEEE Trans. On Electron Devices Vol. 47, No. 12, P. 2320).
A double-gated transistor is operated with fully-depleted channel. Thus, the threshold voltage is not uniquely determined by the channel dosage, and it greatly depends on the width of the channel between two opposed gates. It is thus possible to reduce the channel dosage that determines the threshold voltage, and the above problems may be solved.
The prior art, however, has the following problems.
A method has been proposed, wherein a double-gate transistor is applied to a complex three-dimensional structure of, e.g. a modern integrated DRAM. However, the structure itself is complex and does not permit simple and easy fabrication.
The prior art mainly relates to transistors for logic circuits applied to ASICs, SRAMs, etc. Thus, no description is given of specific structures of DRAMs or necessary characteristics of transistors. In order to apply the fin-gate type double-gate transistor with a simple and easy structure to the DRAM, the problem of insulation between the cell capacitor and cell transistor is important. If insulation at a location under the active word line and insulation at a location under the passing word line are not sufficient, the reliability of the device deteriorates due to erroneous write/read in the memory cell, and the manufacturing yield lowers. Also, the cell transistor must not be disturbed by the voltage modulation of the passing word line.